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Please consider adding the attached PCI chip from
Cypress to the list.
What is the end goal of your list on this webpage?
Product Manager - Multi-ports
Subject: Re: ASIC enquire
Resent-Date: Sat, 24 Jun 2000 09:59:43 -0700
Date: Sat, 24 Jun 2000 11:05:50 -0500
From: David Cary <email@example.com>
CC: Rakesh Malviya <firstname.lastname@example.org>
Dear Rakesh Malviya (and whoever else might be interested),
I've been collecting a list of PCI interface chips at
If you know of any others, please tell me so I can add them to the list.
From: Rakesh Malviya <email@example.com>
To: "'firstname.lastname@example.org'" <email@example.com>
Date: Tue, 23 May 2000 20:20:23 +0530
We are looking for an ASIC for AMBA and PCI Interface Bridge. We will be
grateful to you if you can let us know the vendors ( if any ) who is
providing such interface.
Thanks and Regards
David Cary "mailto:firstname.lastname@example.org" "icbmto:N36 08.830' W97 03.443'"
Future Tech, Unknowns, machine vision ><> <*> O-
Title: Cypress: PCI-DP
SEARCH OUR SITE
(Includes Part No. Searches)
SRAMs & Modules
USB (Univ'l Serial Bus)
Video Chipsets (SMPTE)
Families > Multi-Port
RAMs > PCI-DP
Cypress's Dual Port-PCI
provides a flexible, easy-to-configure interface to a variety of
popular processors, integrating a PCI bridge chip, memory chip and
glue-logic functions in a single-chip solution that reduces system
cost, saves board space, and increases performance. The new chip's
unique architecture leverages Cypress's technological leadership
in multiport memories to meet the needs of high-speed networking
applications such as switches, routers, DSLAMs and cable-modems.
Dual Port-PCI also brings a true dual-ported solution within
reach of more cost-sensitive applications, such as low-end mass
storage and high-end computation.
PCI-DP replaces the
historic DMA/FIFO architecture with a shared memory architecture.
The 128 Kbits of shared memory can be accessed as a target from
either the PCI or local bus. This 128 Kbits can be used as a buffer
for bus master burst reads or writes of any length (up to 128 Kbits
across the PCI bus). The I2O Message Unit provides the FIFOs and
Interrupt Status Registers required to support the I2O protocol.
- 128 Kbits of dual-ported
memory (4K x32)
- PCI 2.2 bus master/slave
interface (33 MHz / 32 bit wide)
- Configurable interface
to allow seamless interconnect to a variety of processors
- Embedded host bridge
- I2O message unit
- 160 pin TQFP package
here to view PCI-DP block diagram
Design Major functions: (full documentation available
- MPC860 PowerQUICC
- 0.5 MByte Static
RAM; 32-bit data; expandable to 2 MByte
- 1 MByte FLASH Memory;
- 32-pin socket for
JEDEC PROM, up to 128 KByte; 8-bit data
- Local Bus designed
for up to 50 MHz; 32-bit data
- 3.3V board design
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on Cypress products plus a free Cypress Data Book CD-ROM, click
on the literature request
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Cypress products, jump to our online store.