PCI Chips

[Jim Dillon <jdx@cypress.com>]

David -
Please consider adding the attached PCI chip from
Cypress to the list.

http://www.cypress.com/dualport/pci_dp.html

What is the end goal of your list on this webpage?

Thanks,
Jim Dillon
Product Manager - Multi-ports
Cypress Semiconductor



Subject: Re: ASIC enquire
Resent-Date: Sat, 24 Jun 2000 09:59:43 -0700
Resent-From: pci-sig@znyx.com
Date: Sat, 24 Jun 2000 11:05:50 -0500
From:  David Cary <d.cary@ieee.org>
To:  pci-sig@znyx.com
CC: Rakesh Malviya <mrakesh@cedt.iisc.ernet.in>

Dear Rakesh Malviya (and whoever else might be interested),

I've been collecting a list of PCI interface chips at
  http://www.rdrop.com/~cary/html/vlsi.html#pci

If you know of any others, please tell me so I can add them to the list.

From: Rakesh Malviya <mrakesh@cedt.iisc.ernet.in>
To: "'pci-sig@znyx.com'" <pci-sig@znyx.com>
Date: Tue, 23 May 2000 20:20:23 +0530
...
Dear Sir/Madam
We are looking for an ASIC for AMBA and PCI Interface Bridge. We will be

grateful to you if you can let us know the vendors ( if any ) who is
providing such interface.
Thanks and Regards
Rakesh


--
David Cary "mailto:d.cary@ieee.org" "icbmto:N36 08.830' W97 03.443'"
  http://www.rdrop.com/~cary/
Future Tech, Unknowns, machine vision ><> <*> O-

Title: Cypress: PCI-DP

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Product Families > Multi-Port RAMs > PCI-DP™

		PCI-DP™
	Data Sheets Application Notes		PCI Web links Press Release

Cypress's Dual Port-PCI™ provides a flexible, easy-to-configure interface to a variety of popular processors, integrating a PCI bridge chip, memory chip and glue-logic functions in a single-chip solution that reduces system cost, saves board space, and increases performance. The new chip's unique architecture leverages Cypress's technological leadership in multiport memories to meet the needs of high-speed networking applications such as switches, routers, DSLAMs and cable-modems. Dual Port-PCI™ also brings a true dual-ported solution within reach of more cost-sensitive applications, such as low-end mass storage and high-end computation.

PCI-DP™ replaces the historic DMA/FIFO architecture with a shared memory architecture. The 128 Kbits of shared memory can be accessed as a target from either the PCI or local bus. This 128 Kbits can be used as a buffer for bus master burst reads or writes of any length (up to 128 Kbits across the PCI bus). The I2O Message Unit provides the FIFOs and Interrupt Status Registers required to support the I2O protocol.

PCI-DP™ Features:

• 128 Kbits of dual-ported memory (4K x32)
  
• PCI 2.2 bus master/slave interface (33 MHz / 32 bit wide)
  
• Configurable interface to allow seamless interconnect to a variety of processors
  (50 MHz)
  
• Embedded host bridge capability
  
• I2O message unit
  
• 160 pin TQFP package

click here to view PCI-DP™ block diagram

Additional Information:

PCI Web Links:

PCI SIG (Special Interest Group) www.pcisig.com

PCI Books www.annabooks.com

PCI Design Resources www.microsoft.com/hwdev

MPC860 Reference Design Major functions: (full documentation available on request)

• PCI-DP™
• MPC860 PowerQUICC Processor
• 0.5 MByte Static RAM; 32-bit data; expandable to 2 MByte
• 1 MByte FLASH Memory; 8-bit data
• 32-pin socket for JEDEC PROM, up to 128 KByte; 8-bit data
• Local Bus designed for up to 50 MHz; 32-bit data
• 3.3V board design

Multi-Port RAM Products

NEW! PCI-DP™

QuadPort™ RAM

FLEx36 Dual-Port RAM

1-Mbit Dual-Port RAM

Low-Voltage Synchronous Dual-Ports

Low-Voltage Asynchronous Dual-Ports

5-V Synchronous Dual-Ports

5-V Asynchronous Dual-Ports

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