A PC can judge a slot is unoccupied if there is no request to Read Config
It means for FPGA's based PCI controller your FPGA must be ready before the end
of PCI Reset.
The available time to load your FPGA depends of platforms :
Spec 2.2 platforms : RST# High to First configuration Access => 2^25 clocks (~ 1 sec @33 MHz)
Spec 2.1 and earlier : as soon as possible after RST_N goes high. The
spec has a minimum
of 1ms "Reset active time after power stable". Most of RST signals are asserted during
100ms to 500ms .
In any case, this available time is quite short for large FPGAs.
Daniel DeConinck a écrit :
Hello, Regarding: PCI CLKs turning off in unused slots. Can a PC incorrectly judge a slot to be unoccupied if that slot contains a FPGA controller which needs some time to configure ? OR do PCs always only use the 'card present' signal to determine if a slot is occupied. SincerelyDan DeConinck
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