RE: PCI CLKS disabled relating to FPGA controllers ??

["Olaf Birkeland" <Olaf.Birkeland@fast.no>]

Hi Marco,

I've got a program that will do what you need. It's only running under DOS
though, as we use it for real low-level debugging (it even tosses out DOS
when loading to get a 4GB linear address space.....) Let me know if this
would be to any help for you. I could then remove the functionality that is
specific to our products and send you a copy.

The function you need is access to PCI configuration space within the
bridges. This is easily done through the PCI BIOS. First do a PCI scan do
find all bridges (by either the FIND_PCI_DEVICE or FIND_PCI_CLASS_CODE BIOS
functions), and use the returned bus/device/function numbers to access the
bridge registers. You'll find the specifications for this on pages 9-17 in
the pink "PCI BIOS Specification" you've probably received from PCI SIG.

Regards,
- Olaf

> -----Original Message-----
> From: marco@eux100.sgp.st.com [mailto:marco@eux100.sgp.st.com]On Behalf
> Of Marco Brambilla (Wireline)
> Sent: 29. juni 2000 18:22
> To: pci-sig@znyx.com
> Cc: pci-sig@znyx.com
> Subject: Re: PCI CLKS disabled relating to FPGA controllers ??
>
>
> Hi everyone, and thanks to all thos (you were really lots) that dropped
> their mails.
>
> To recap the latest findings:
>
> - the newer motherboards (actually the PCI2PCI bridge) can disable the
> clock for individual slots if the slots themselves are not occupied. The
> bridge usually has N clk outputs, one for every slot, so no additional
> logic is required. An example of this is
> http://developer.intel.com/design/bridge/datashts/27810601.pdf
>
> (thanks to Leif Erik Laerum for pointing me to the file)
>
> In our specific case we have a device that during the debug phase cannot
> be programmed until after the PC finishes the boot phase.
>
> At power on reset the bridge chip will reset the clock disable bits,
> then it will be the CPU that will do a bus scan and disable the slots
> where no devices are present.
>
> This reset is only done at power on, so in order to have your clock back
> you cannot simply do a reset of the machine, but you must write a
> register in the config space of the pci bridge.
>
> When detection fails for a production FPGA device that could mean that
> either
> - the PC doesn't wait for the pci 2.2 one second "boot" period for pci
> devices (on our board the clock is seen present even on empty slots - no
> boards at all - for some seconds, where some was not precisely measured,
> but is 2 - 5.
>
> - the fpga takes longer than 1 second to load after power good
>
>
>
> Our last problem is that although we have a pci bus excerciser, we
> cannot access the clock enabling register, because the configuration
> space of the bridge can only be accessed from the primary bus.
>
> So we now just need to understand how to access, via BIOS or whatever,
> the configuration space of the pci bridge.
>
> Thanks for your support and patience.
>
> Marco.
> --
> --------------------------------------------------
>  Marco BRAMBILLA
>
>  STMicroelectronics
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>
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