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Re: Possible to limit size of DMA transfer?
Under normal operating conditions, the length of
access is determined by the Master Latency Timer (MLT)
of the master device. The value specified in the MLT
register is the minimum number of PCI clock cycles
that the master is guaranteed access to the bus. This
value is programmable. It is accessed as a PCI config
--- Andy Davenport <ANDY@THUBAN.AC.HMC.EDU> wrote:
> I have a video capture card with the Conexant (nee
> BrookTree) Bt878
> chip. I am getting horizontal line defects across
> the video that I
> believe are due to overruns in the rather small FIFO
> in the Bt878.
> My reading of the chip spec says that I have only 10
> to 13 usec to
> gain access to the PCI bus before losing video
> samples. I also have
> an Adaptec 2940U2W SCSI on the same PCI bus to which
> are attached
> the disks for saving the video data. My presumption
> is that the
> 2940U2W grabs the PCI for far longer than 13 usec
> (as it rightly
> should for efficiency, I suppose) and I lose video
> data. Even a
> lowly 2048 byte transfer would take more that 15
> usec, right?
> So my questions are:
> Is there anything in the PCI spec that provides
> for imposing
> a bus-wide limit on the size of DMA transfers? If
> so, is there
> any means in Windows NT to cause such a limit to
> be imposed?
> Failing that, is there some kind of registry key
> for maximum
> DMA transfer size in WinNT that is observed by PCI
> Failing that, does anyone know if Adaptec has a
> way of imposing
> such a limit on its own adapters?
> As a parting shot, just out of curiosity, is PCI
> bus tuning
> (trading off access latency, bandwidth etc)
> something that is
> commonly done, or for which there is any existing
> Thanks very much.
> Andy Davenport
> Harvey Mudd College
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