Hot-swap and Reset Trhfa

[Lame Brooks-G14738 <brooks.lame@motorola.com>]

	I think I goofed a little in my previous message on this subject.
In the Terminology section of the PICMG 2.1 HS spec, it had appeared that
state H2 was synonomous with state S0.  Getting more intimate with the
Hot-swap spec, state H2 is defined strictly as the device electrical,
PCI_RST# deasserted, buffers un-tristated, connected to the CPCI bus (&
other required busses) condition.  S0 includes the definition that the board
is accessible in PCI configuration space.  So, it follows that Trhfa
(2^25clks) should be the maximum time from state H2 to state S0, _not_ from
state H1 to state H2 as previously written.  
	  Further, between H2 and S0, the peripehral should respond to
accesses as described in PCI 2.2, sec 4.3.2 (same as ECN to 2.1) - either no
response, retry, or access accepted and data valid.  
	Comments?
-- BrooksL