Clock design / spread spectrum question

[Klaus Bahner <kgb@tcelectronic.dk>]

Hi folks!

Quite often in integrated  PCI/microcontroller chips, the PCI bus clock
is directly used as clock base for the whole system. All other clocks,
like processor and memory clocks, are derived from the PCI clock by
means of PLLs. In particular I'm thinking about Motorolas 8240, which
also claims to be capable of a 66 MHz PCI bus clock.
However, I wonder if such a design is valid in 66 MHz system, where
spread spectrum clocking may be enabled. I'm not an expert on PLLs, but
my guess would be that a PLL can't handle the "jitter" of spread
spectrum clocking.

Any thoughts on this?

Best regards,
Klaus Bahner