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RE: Clock design / spread spectrum question



>I'm not an expert on PLLs, but
>my guess would be that a PLL can't handle the "jitter" of spread
>spectrum clocking.

That depends on the bandwidth of the PLL relative to the modulation
frequency (how rapidly it jitters), and the amount of jitter modulation (how
far the clock frequency changes).  See section 7.6.4.1 in the PCI Spec
version 2.2, especially the "Implementation Note: Spread Spectrum Clocking
(SSC)" on page 227.

The allowed spread spectrum jitter allowed for 66 MHz PCI is fairly small
(-1 to +0% ... note the typo in Table 7-3).  A properly designed PLL can
handle it.  A poorly designed one might not.