Of course, the "correct" way to do this is with a PCI-to-PCI bridge. They your design should work in any system.
In the early days of PCI I was involved with a board that had two devices on one board without a bridge. We were forced to go that way for a number of reasons I won't go into here. But, it did work in widespread applications with a large number of end-users (10,000+) that retrofitted it into computers that they already owned. There were very few (if any) problems caused by our non-compliant design. I found that the PCI bus was very robust. We even had some users plug two of our boards into the same system and have it work without problems! With newer ICs, there is probably even more margin on PCI timing parameters than there was then. It won't hurt to watch your layout closely and make sure that you end up with a daisy chain instead of stubs (you might as well give your design the best chance of working), but I'd bet it would work even if you didn't. Our design had two chips on the same side of the board (on at the bottom edge and one at the top) and violated the trace length spec. In addition to that, the original designer didn't realize the clock spec was tight and just had it routed to the two devices without concern for length matching (like I said, I found PCI was very robust).
The one thing that will be a little bit of a trick is the IDSEL. There is only one provided by the PCI connector. You will need to make another for the second chip. The PCI-to-PCI Bridge Architecture Specification (rev 1.1) shows in chapter 3 (table 3-1) how the PCI bus generates IDSELs from AD lines. When you tie an IDSEL pin to an address line you will make a new "slot" and you need to make sure that you don't contend with a real slot. Early on, we did this with a header that allowed us to select our "slot" number with a jumper. Later we had a PLD that, with software help, automatically selected which "slot" was safe to use.
Sent: Tuesday, July 18, 2000 7:00 AM
Subject: two loads on a single connector ?
The biggest thing i would pay attention to is the motherboard, and the
topology of the PCI bus you desire. If you place your dual-PCI-Agent board
at one end of the PCI bus (make sure it is really the end, and there are no
chips off the end of the bus, on the motherboard!), the two parts look like
an extension to the bus rather than two clustered loads in the middle of
the bus. PCI may be more well-behaved that way. In addition, if you were to
so constrain this, it would not really be necessary to pay attention to
trace length constraints to one of the Agents, since you would be adding to
the total bus length, not introducing a stub. In addition you would be best
to lay out your board so that there are no tees in the PCI routing; each
PCI line runs in a daisy-chain from the connector, to one PCI Agent, then
directly to the other PCI Agent (which could be centimeters away).
Granted that this is not ideal (a note for the purists out there....), but
i feel it stands the greatest likelihood of working.
The above are opinions of the author, and not necessarily those of Rockwell
----- Forwarded by Frank M Nemeth/CedarRapids/Collins/Rockwell on 07/18/00
08:42 AM -----
Kal" To: email@example.com
.st> (by way Subject: two loads on a single connector ?
The question I have is whether I can use two loads on a single board.
This board will run only in a controlled environment and will be the
only board (at most one other) in a 4 slot PC motherboard. The problem
is that I need to talk to one chip which has a PCI connection and a CPU
connection. I need to connect an FPGA to the CPU bus of the chip and the
FPGA has to reside on PCI too. I don't want to design two boards and use
a ribbon cable to do the connection. What should I pay attention to in
a system like this ? I am thinking about putting the two PCI chips on
different sides of the board ? This should let me meet the trace length
constraints. Is this a viable solution ? Again this board will exist in
a controlled environment where not all the slots will be filled.