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PAR64 location

Hi,
My name is Ronnen Lovinger, IO and package Engineer For Mellanox
technologies.

while planning the pad location for the PCI, I have found 2 contradicting
places in the 
rev2.2 for the par64 pin location.

Figure 4.9 shows a QFP pci component, in which PAR64 is the last pin on the
left. (I would believe
the routing would be pin to pin with the connector  in this type of package)

Looking at the pinout of the connector (table 4-13) par64 is located between
cbe2 and ad62.

what is the correct location for the par64 pin?

thanks, 
Ronnen Lovinger