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Re: pci9080 chip



We had similar problems with the PLX9054. The  computer hangs within the boot
sequence.
The solution was to pull down READYI#. If the target is not ready
(READYI#=VCC), the 9054 performs retrys and the computer hangs.
Kind regards
Stephan Gick


Masaru Naganuma schrieb:

> Harkema,
> You should tie NB# to GND if there is no EEPROM.
> If not, 9080 expect to configure from local processor.
> ------------------------------------------------------------
> Masaru Naganuma for edec co.,ltd. <naganuma@edec.co.jp>
>
> ----- Original Message -----
> From: "Harkema, G.A." <G.A.Harkema@tue.nl>
> To: <pci-sig@znyx.com>
> Sent: Thursday, July 27, 2000 2:44 PM
> Subject: pci9080 chip
>
> > Hello,
> > we are developing a PCI board to controll a data aquasition system. On
> > the PCI board is the PCI9080 chip. On the local bus of the PCI9080 is
> > only a I/O controller whitch is implemented in a FLEX7000 EPLD from
> > Altera. There is no EEPROM placed on the board. We are using the PCI
> > chip in "C mode". Local bus input signal lines have the following signal
> > levels:
> > ADMODE             = VCC
> > BIGEND#               = VCC
> > BREQ                    = GND
> > DREQ[1:0]#          = VCC
> > LRESETI#             = VCC
> > NB#                     = VCC
> > S[2:0]                  = GND
> > WAITI#                = VCC
> > BTERM#              = VCC
> > LLOCK#                = VCC
> > LHOLDA              = GND
> > EOT0#                   = VCC
> > EOT1#                   = VCC
> > READYI#                = VCC
> > LINTI#                  = VCC
> >
> > All tri-state I/O pins except LD[31:0], LA[31:2] and LBE[3:0]# have a
> > pull-up resistor to VCC (10k), all tri-state I/O from the EPLD is
> > permently disabled.
> >
> > All PCI bus signals are connected to the PCI bus (PCI bus = 32 bit, 33
> > MHz, 5 V).
> >
> > The local bus clock frequency is 20 MHz.
> >
> > When booting the computer system we see the following:
> > LRESET0# goes low for about 160 ms.
> > After this the EESK clock starts and the EECS goes high.
> > After 11 EESK clocks EECS goes low and after 13 EESK clocks EESK stops
> > clocking.
> > ??? what is happening according the datasheet of the PCI9080, page 117,
> > EESK is a continous clock ???
> >
> > During EEPROM initialization the PCI9080 respons on the PCI bus as a
> > disconnect.
> > ??? according the datasheet page 14 is should respons as a retry ???
> >
> > After a while (we dont now how long) the respons to the PCI bus is a
> > retry, and the computer system hangs (in the boot sequence).
> > ??? why is respons of the PCI9080 chip to the PCI bus a retry, the
> > EEPROM is not loaded and the NB# pin is connected to ground ???
> >
> > Please help us.
> >
> > Kindest regards
> >
> > Gerard A Harkema
> >
> >
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