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PCI compliance for tristate output buffers
We would appropriate comments and information regarding the following electrical
compliance requirement on PCI tristate output buffers:
1. Maximum AC ratings for 3.3v signaling environment (SPEC 2.2 184.108.40.206, p.125) -
a. Is this a compliance requirement to perform the actual tests on the
device, or the reliability of the device can be "guaranteed by design", (what
kind of simulation)?
b. If real tests are needed, where can we find instrumentation that provides
voltage source impedance of 29ohms & 28ohms (Fig. 4-5), and where can we locate
vendors that can perform these tests?
2. AC specifications for 3.3v signaling environment (SPEC 2.2 220.127.116.11, p.123):
output rise/fall slew rates -
a. Test conditions for output slew rates specify loads as illustrated in the
diagram, but footnote 3 says it is optional. And PCI Compliance Checklist
Rev.2.2, p. 21, CE33 & CE34 ask for UNLOADED rise/fall times. Is it sufficient
to measure the slew rates without the loads, using the same test limits?
3. PCI Compliance Checklist Rev.2.2, p. 20, CE26 & CE28 - max output source &
a. Are the 115mA at 2.5V & 137mA at 0.65V requirement derived from Equation C &
D from SPEC 2.2 18.104.22.168, p.123&124? Are the specified currents instantaneous or
steady state currents? Any standard methods to measure them? Is simulation alone
sufficient to meet compliance?