[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: <= 8 byte operations, with 64-bit PCI master


I worked on a 64 bit PCI host bridge design some time ago.  My recollection
is that we did not attempt 64 bit transfers for host initiated writes
unless the write was for more than 8 byte.  In other words, what you
describe below sounds exactly the same as what we concluded.

Monish Shah
Ascent Software

----- Original Message -----
From: Kevin Normoyle <Kevin.Normoyle@Eng.Sun.COM>
To: <pci-sig@znyx.com>
Sent: Saturday, August 05, 2000 4:19 AM
Subject: <= 8 byte operations, with 64-bit PCI master

> The pci 64-bit extension has this funky method for negotiating
> 64-bit transfers.
> It leads to the interesting case for 8 byte or less transfers
> where a 64 bit master talking to a 32-bit device is less
> efficient, compared to just doing 32-bit transfers right
> off the bat.
> Also, when the 64-bit pci master is doing a write
> to an odd 32-bit address, the behavior is a little different
> for the target, and it raises questions of whether it
> might expose a bug, say for a 4 byte stores to an odd 4-byte
> address (say 0x4).
> For instance, people may have taken shortcuts in implementing
> writes to a CSR.
> A mem space write may be expected to have the CSR address (0x4)
> as the PCI address,
> instead of starting with an 8 byte aligned address (0x0), and
> getting to the 0x4 with an extra data beat.
> If the card was only tested with 32-bit masters, it might
> never have been exposed to the required behavior.
> (except in simulation)
> Since there is no performance benefit to doing 64-bit attempts
> for <=8 bytes (even with 64-bit target), and 32-bit only is required
> for IO space, I'm wondering if it makes sense to only
> attempt 64-bit transfers for >8byte bursts. (for MEM space)
> What do other people do? Any experience?
> Do other 64-bit masters go thru the 64-bit attempt even
> for <=8 bytes? Have any target cards broken because of this?
> (due to having a bug)
> -kevin