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C/BE[3:0] - PCI traget implementation
Hello,
I have designed a PCI target which only executes
two commands.
C/BE3# C/BE2# C/BE1# C/BE0#
Memory read
0
1
1 0
Memory write
0
1
1 1
On a new FRAME I latch the command nibble. I
only decode the three LSbits. I ignore C/BE3#. I felt that this would be
acceptable since only these two commands would be executed at the address where
my board is located. (DC00 in the bottom one meg) I am wondering if this can get
me into some unforseen trouble ?
My card seems to work fine. It crashes when another
PCI card is in MASTER mode doing a DMA to main memory and simultaneously the CPU
tries to read my card.
I use an XCS20-4PQ208C for my PCI
interface.
Sincerely
Daniel DeConinck