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Re: C/BE[3:0] - PCI traget implementation

Daniel,
 
it will definitivelly cause some trouble:
 
1) there may be IO and config accesses that may use the same address that your board uses. You may not respond to these cycles.
 
2) You must respond to Memory read Line/Memory read multiple and Memory Write and Invalidate commands if you implement PCI memory. You may treat this commands like simple Memory read and Write commands internally, but you have to respond to these commands.
 
Regards,
 
Peter Marek
General Director
MarekMicro GmbH
Kropfersrichter Str. 6-8
D-92237 Sulzbach-Rosenberg
Germany
Phone: 049 - 9661 - 908 - 210
Fax:      049 - 9661 - 908 - 100
----- Original Message -----
From: Daniel DeConinck
To: pci-sig@znyx.com
Sent: Tuesday, August 08, 2000 11:22 PM
Subject: C/BE[3:0] - PCI traget implementation

Hello,
 
I have designed a PCI target which only executes two commands.
 
                    C/BE3# C/BE2# C/BE1# C/BE0#
Memory read       0          1           1           0
Memory write       0          1           1           1
 
 On a new FRAME I latch the command nibble. I only decode the three LSbits. I ignore C/BE3#. I felt that this would be acceptable since only these two commands would be executed at the address where my board is located. (DC00 in the bottom one meg) I am wondering if this can get me into some unforseen trouble ?
 
 
 
My card seems to work fine. It crashes when another PCI card is in MASTER mode doing a DMA to main memory and simultaneously the CPU tries to read my card.
 
I use an XCS20-4PQ208C for my PCI interface.
 
 
Sincerely
Daniel DeConinck