RE: Memory Write and Invalidate

["Tisani, Mohamad" <MTisani@pericom.com>]

Neal 

i have seen a major improvemnts on MRL/MRM

MRL will allow the bridge for example to prefetch up to the CLS

But for MRM it can prefetch for lage values i have seen burst using Pericom
Semiconductor Corp  three port PCI to PCI Bridge of up to 300 DWORDS 
this can really boost your Performance . The bridge will go through flow
Through mode and will continue to xfer data as long as the target is
providing data 

I really recommend for you to use MRM , just make that this does not have
side effect for your application 

--------------------------------------------------------------------
Mohamad Tisani                       Tel     :  408 435 0800   x 347
                                     Pager:  800 490 3854
Director, Application Engineering    Fax   :  408 435 1100              
Pericom Semiconductor Corp.          Email: mtisani@pericom.com


-----Original Message-----
From: Neal Palmer [mailto:neal@dinigroup.com]
Sent: Monday, August 14, 2000 10:04 AM
To: Duane Clark
Cc: pci-sig@znyx.com
Subject: Re: Memory Write and Invalidate



I'm interested in the MWI question as well.

For MRL/MRM there is a decided advantage to using it, especially on the
64/66 PCI busses on new motherboards.  I have seen a difference of about
50% bandwidth useable on PCI when reading host SDRAM.

On Fri, 11 Aug 2000, Duane Clark wrote:

> Howdy,
> 
> I was interested in any experience or info folks have with using memory
> write and invalidate in a bus mastering add-in card. Has anyone found
> that implementing this confers a performance advantage over normal write
> transactions in common real world platforms (X86)? How about high end
> platforms? Similarly, how about the memory read multiple and line
> commands?
> 

-- Neal Palmer

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