looking for Parity signal status

[nimit.endlay@st.com]

I am working on the Parity Block of a PCI COre.

I am facing problem in deciding what should be the status of PAR,ie, 

a)last parity should continue ,or
b)the PAR signal shoul be tristated, or 
c)a new parity be generated 

when C/BE has changed but the old Data continues due to wait state
inserted by 
i)the initiator during a write transaction ,or
ii)by the target during a read transaction ,or
iii)by both at the same time

Thanks,
Nimit