Re: looking for Parity signal status

["Peter Marek" <peter.marek@marekmicro.de>]

PAR will always be the parity across AD31:0 and CBE3:0 with a 1 clock cycle
delay....

Regards,

Peter Marek
General Director
MarekMicro GmbH
Kropfersrichter Str. 6-8
D-92237 Sulzbach-Rosenberg
Germany
Phone: 049 - 9661 - 908 - 210
Fax:      049 - 9661 - 908 - 100
----- Original Message -----
From: <nimit.endlay@st.com>
To: <pci-sig@znyx.com>
Sent: Tuesday, August 22, 2000 7:29 AM
Subject: looking for Parity signal status


> I am working on the Parity Block of a PCI COre.
>
> I am facing problem in deciding what should be the status of PAR,ie,
>
> a)last parity should continue ,or
> b)the PAR signal shoul be tristated, or
> c)a new parity be generated
>
> when C/BE has changed but the old Data continues due to wait state
> inserted by
> i)the initiator during a write transaction ,or
> ii)by the target during a read transaction ,or
> iii)by both at the same time
>
> Thanks,
> Nimit