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Re: looking for Parity signal status
Nimit: You're not allowed to change C/BE during
wait states caused by irdy/trdy.
Some pci parts have done this and caused parity errors,
notably thru bus bridges or any part that sample the C/BE only
during the first cycle of a stalled data beat.
Do people agree?
> I am working on the Parity Block of a PCI COre.
> I am facing problem in deciding what should be the status of PAR,ie,
> a)last parity should continue ,or
> b)the PAR signal shoul be tristated, or
> c)a new parity be generated
> when C/BE has changed but the old Data continues due to wait state
> inserted by
> i)the initiator during a write transaction ,or
> ii)by the target during a read transaction ,or
> iii)by both at the same time