Data Parity Error Recovery

["Madhura Bokil" <madhura@controlnet.co.in>]

Hello,

  After going through the PCI-X Addedum Rev. 1.0, I have some doubts. I will be thankful if anyone clarifies them.

This is regarding the SERR# assertion during Data Parity Error.[Ref. 5.4.1 pg.no.121-122]

There it is mentioned that, if the Data Parity Error Recovery Bit is cleared [i.e. system can not recover from data parity error], SERR# is to be asserted.

The doubt is : for assertion of SERR# [the clock on which SERR# is asserted], whether it should follow PCI2.2 std. or PCIX std.?

                     whether the assertion of SERR# is to be reported in status register? If yes, which bit?[SERR# detected or PERR# detected]

                     whether PERR# also is to be asserted?

Madhura.