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Re: Intel chipsets and prefetch during PCI target read
A PCI slave device is mapped to uncached memory, and with IA32 CPUs reads
to uncached memory are blocking, that is, a read can't emerge from the CPU
until a previous read completes. Consequently the largest burst is limited
to the largest single read, which is the 64 bit MOVQ r64, mem instruction
for a two beat burst. You can improve read throughput over that of 32 bit
reads by using this instruction in a tight loop, but of course this still
won't approach performance that can be realized with our PCI master chips.
Technical Applications Engineer
PLX Technology, Inc.
At 11:53 AM 8/23/00 -0700, William F Hong wrote:
>The system we are developing contains a homegrown, target only, PCI ADC
>card which uses a PLX Technologies 9050 PCI interface chip. Our
>application requires that the contents of the ADC sample memories be read
>rapidly to system memory. Using a bus analyzer I have observed that our Intel
>440BX Host/PCI bridge generates a single PCI Memory Read transaction
>for each 32-bit Dword that the Pentium requests even though the reads are
>to consecutive ADC memory locations. Isn't the 440BX capable of doing any
>prefetching, i.e. generating a PCI burst read in anticipation? I know
>PCI target can support burst reads because I have used the bus analyzer as
>a master and performed the same transfer. After reading
>related posts in the PCI Reflector Archive I find two different answers.
>Some say that north bridges can do prefeching from capable PCI targets (target
>contains prefechable and cacheable memory) others say that north bridges are
>incapable of generating burst reads from PCI. An Intel Customer Support
>on the Intel Chipset Forum indicates that none of their chipsets have this
>capability. I would like to resolve these contradictions before I tell
>designers that we can only achieve the desired PCI to Host throughtput by
>redesigning their boards with PCI master capability. So assuming that the ADC
>cannot be redesigned...
>1) Can the time between reads by the processor affect the Intel 440BX's
> to do a prefetch, i.e. is my Windows NT driver too slow?
>2) If the Intel 440BX chipset cannot prefetch PCI data are there any
> (Intel or other) for Pentium systems which can?
>3) Does anyone know of another mechanism to transfer data from a PCI
> system memory which takes advantage of PCI burst cycles?
>4) I understand that target memory prefechable is set in the base address
> of the PCI target's configuration space only if the target memory
> prefech has no
> side effects. But what does it mean in this context to be cacheable?
>Thanks in advance.
>Raytheon Missile Systems