Is it a PCI specs violation that ...

["Weng Tianxiang" <wtx@umem.com>]

Hi,

I am designing a system located on PCI Bus 0 and designed a data and command mixed transfer mechanism as follows, I want to confirm whether or not my such practice is a violation of PCI specs:

 

In device PCI configuration, I use a Base Address Register and apply for 1KBytes for command and status use only.

 

Now I design a command that has a command head and data part. The data part is far beyond the 1KBytes. When handling the situation, I know where the data part starts and will transfer its data part into internal memory. But from PCI Bus point of view, its final address is far beyond the 1KBytes space, and possibly it steps into other device memory space.

 

Becasue PCI transaction is recognized only at its address cycle, so I think if the first address falls into my memory space, others will ignore any amount of data transferred.

 

Thank you.

 

Weng