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Re: pci-x query
Bus and device numbers are read-only with regard to
accessing them directly with a config write cycle.
However, due to the fact that a config write cycle (as
well as other PCI-X cycles) contains the bus and dev
number. Therefore these registers are automatically
>From 6.2.4 of PCI-X 1.0
"As described in Section 7.2.4, each time the device
is addressed by a Configuration Write transaction, the
device stores the device and bus number from the
configuration address and attributes (see Section
22.214.171.124) in the registers."
--- Madhura Bokil <email@example.com> wrote:
> I have some queries regarding PCI-X.
> 1] This is regarding the PCI-X status register.
> [Pg. 141 from PCI-X Addendum Rev. 1.0]
> Bits 15-8 [Bus Number] & 7-3 [Device Number]
> are mentioned as Read-only bits in the standard. At
> the same time it is mentioned that these bits should
> be updated
> during each Configuration Write Transaction.
> If these bits are to be updated during every
> Configuration Write transaction, how these bits can
> be read-only?
> 2] This is regarding the split response during
> DWORD transactions.
> I am not getting the significance of the
> Split Response for DWORD transaction. If it is a
> DWORD transaction, why it is necessary to give split
> response instead of
> completing the transaction?
> I will be thankful if somebody can help me to clear
> these queries.
> Madhura Bokil.
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