Search for generic PCI Master/Slave VHDL/Verilog Model

["John D. Cappello" <jcappello@optimal-design.com>]

Dear PCI-SIG,

I am developing a testbench for a design that includes a PCI
initiator/target that allows the design to interact with a 32/64-bit 66
MHz PCI bus. Do you know of any off-the-shelf generic PCI master/slave
models (VHDL or Verilog) that would automatically generate the low-level
PCI signaling from a higher level description of read and write cycles?

The idea here is to simply exercise the PCI bus so that the design under
test can be accessesd under a range of conditions, not to exhaustively
test the PCI initiator/target in the design. My fallback plan is to
create the PCI agent using previous experience with similar models.

Thank you.

John Cappello
Optimal Design, Inc.
856-582-4838
jcappello@optimal-design.com