Is there a host bridge retry counter in the chipset and what is the count limit ?

[William Wu <wwu@sebringnetworks.com>]

It was suggested in the following book "PCI System Architecture", 3rd
edition, MindShare, Inc., Tom Shanley/Don Anderson
(chapter 9 premature transaction termination) that the host bridge should
have a host bridge retry counter (not a requirement).
The counter is reinitialized every time a transaction is completed.  Each
time the bridge experiences a retry, the counter is
decremented.  When the counter reaches zero, it should stop retrying.  It
should return dummy read data if it is a read and drop
the write data .... and then assert interrupt to the CPU ..

Is there any host bridge chipset that implement such counter (not in PCI
spec.) ?  If so, what is the lower limit, upper limit and default values ?

William S. Wu
PLX Technology, Inc.
200 East Hacienda Ave. 
Campbell, CA 95008 
Phone: 408-871-7409 
Fax: 408-374-2652