RE: Is there a host bridge retry counter in the chipset and what is the count limit ?

["Olaf Birkeland" <Olaf_Birkeland@hotmail.com>]

> -----Original Message-----
> From: William Wu [mailto:wwu@sebringnetworks.com]
> Sent: 5. september 2000 20:42
> To: 'pci-sig@znyx.com'
> Subject: Is there a host bridge retry counter in the chipset and what is
> the count limit ?
>
>
>
> It was suggested in the following book "PCI System Architecture", 3rd
> edition, MindShare, Inc., Tom Shanley/Don Anderson
> (chapter 9 premature transaction termination) that the host bridge should
> have a host bridge retry counter (not a requirement).
> The counter is reinitialized every time a transaction is completed.  Each
> time the bridge experiences a retry, the counter is
> decremented.  When the counter reaches zero, it should stop retrying.  It
> should return dummy read data if it is a read and drop
> the write data .... and then assert interrupt to the CPU ..
>
> Is there any host bridge chipset that implement such counter (not in PCI
> spec.) ?  If so, what is the lower limit, upper limit and default values ?
>
I don't know anbout host bridges, but at least the Intel/Dec PCI/PCI bridges
implement a fixed max retry count for delayed reads/writes of 2^24. After
this a target abort will be signalled to the initiator.

Regards,
- Olaf