Re: PCI Burst Length Limit

["Mikhail Matusov" <matusov@squarepeg.ca>]

> You only have 2 clock cycles to write the next piece of data into the
> local side of the s5933 once it has started writing data to the PCI bus.
> If you wait any longer than 2 clock cycles, then it will assume that there
> isn't any more data, and it will terminate the burst.

I think the question was about the other direction even though it was called
a "master write" in the text. In fact, we are talking about target write and
the burst length is limited by I believe the 440BX chipset. This topic was
discussed on the list several times.

============================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: 1 (613) 271-0044 ext.231
Fax: 1 (613) 271-3007
http://www.squarepeg.ca

>
>
>
> On Thu, 7 Sep 2000 olivier.stehlin@wifag.ch wrote:
>
> > Hi
> >
> > I am doing tests with a prototyping board for the AMCC S5933. When doing
> > PCI-master-writes (PC -> add-on-card), I noticed that burst length is
never
> > greater than 8 clocks. I have checked the latency timer, the PC-program
has
> > always enough data (same buffer in a loop), the add-on-card reads data
> > synchronous with the PCI-clock.
> >
> > What can I do to increase the burst length ?
> >
> >
> > My configuration:
> > Dell Optiplex GX1
> > Pentium II, 350 MHz, 440BX
> > Phoenix BIOS 07/27/98
> > WinNT4.0, SP4
> >
> >
> > O. Stehlin
> >
> > mailto:olivier.stehlin@wifag.ch
> >
>
> -- Neal Palmer
>
> The Dini Group
> 1010 Pearl St #6
> La Jolla, CA 92037
> (858) 454-3419 x16
> (858) 454-1728 (Fax)
>
>