PCI Burst Length Limit (clarification)

[olivier.stehlin@wifag.ch]

Thank you all for your answers.

I apologize for the bad fomulated question and I try once again:

Data transfer go from the PC to the add-on card. The AMCC S5933 is the bus
master and reads the data from the PC memory and puts them in its 8-DWORDs
FIFO. This FIFO can never be full, because it will immediately be read with
33 MHz.

To be sure :

Will the cache line size in this particular situation be the limiting factor
?

In this case, the absolute maximal throughput is half the PCI-Bus
theoretical throughput ?

Is the only workaround, to buy a non-intel PC ? Which one ?



O. Stehlin

mailto:olivier.stehlin@wifag.ch