Re: PCI Burst Length Limit (clarification)

["Weng Tianxiang" <wtx@umem.com>]

Hi Olivier,
You are using Master mode from AMCC S5933 to do read and try to get highest
data throughput:
1. Check whether AMCC S5933 can generate Memory Read Multiple command. If it
can, you cannot do anything except selecting a different motherboard to try.
If it cannot, change to other chips. From PCI card designer's point of view,
what a designer can do to achieve your goal (almost every board designers'
goal) is to use Memory Read Multiple command to read block of data and avoid
inserting waiting cycles.

2. There is an excellent article to answer almost all your questions in the
following website:
 http://support.intel.com/support/chipsets/pc1001.htm
This article describes the situations that two different NIC cards (Network
Interface Cards) show totally different PCI efficiencies when they use only
Memory Read or Memory Read Line commands.

Weng



----- Original Message -----
From: <olivier.stehlin@wifag.ch>
To: <pci-sig@znyx.com>
Sent: Friday, September 08, 2000 2:10 AM
Subject: PCI Burst Length Limit (clarification)


> Thank you all for your answers.
>
> I apologize for the bad fomulated question and I try once again:
>
> Data transfer go from the PC to the add-on card. The AMCC S5933 is the bus
> master and reads the data from the PC memory and puts them in its 8-DWORDs
> FIFO. This FIFO can never be full, because it will immediately be read
with
> 33 MHz.
>
> To be sure :
>
> Will the cache line size in this particular situation be the limiting
factor
> ?
>
> In this case, the absolute maximal throughput is half the PCI-Bus
> theoretical throughput ?
>
> Is the only workaround, to buy a non-intel PC ? Which one ?
>
>
>
> O. Stehlin
>
> mailto:olivier.stehlin@wifag.ch
>
>