Re: FFs for GNT and REQ

[iachetta@us.ibm.com]

>>would I violate the PCI Spec when I add flip-flops to GNT and REQ
>>lines of an arbiter?  (in other words the arbiter sees the REQ signal
>>delayed by one clock and the master requesting the bus sees the GNT
>>signal also delayed by one clock)
>
>I don't see a problem for REQ# (although it may not be nice to assert
>request and then not take the bus).  Anyway, I assume that an arbiter
>would be able to cope with that situation (potentially arising at the
>end of a transfer).
>
>It is, however, certainly critical for GNT#.  You may only assert
>FRAME# when GNT# is detected asserted - and this may no longer be the
>case one cycle later.  Therefore I don't think your idea works for
>GNT#.

Stefan, I agree with what you are saying but it sounds like he is asking
about an arbiter design, not a master design.  I can't think of any reason
why the arbiter itself could not latch the req and grant lines provided all
masters sample gnt# live.

Rich Iachetta
IBM Microelectronics Division -- Austin
World Wide Field Design Center
Phone: 512-838-6305   Tie Line: 678-6305