RE: Question about PCI 2.2 spec and 3.3V signaling

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> I am new to designing PCI cards and am trying to figure out a few things
> about
> the PCI spec.  First, just to clarify that I am reading the spec
> correctly,
> having a 3.3V card just means that the signaling on the PCI bus is at 3.3V
> vs
> 5V, not that all the IC's on the card need to work at 3.3V right?
 
Right.

It really means that the signaling of the PCI signals (through the
connector) conforms to one or the other set of specs, which also has to do
with drive strengths, overshoot clamps, input thresholds, etc.  "5V
signaling" does not necessarily mean the signals actually go to 5V.  3.3V is
adequate, even 2.4V is OK.  (Remember TTL?)  But in the 5V environment, the
pins must not clamp at 3.3V, like ordinary 3.3V CMOS outputs would.


> However, I
> suppose it would be ideal to have all (or at least mostly) chips that work
> with
> a Vcc of 3.3V?  
 
That's entirely up to you; PCI doesn't care.  PCI defines the electrical
interface at the card's finger pins.  5V power is always available for those
chips that need it.

However, having a mixed Vcc environment does tend to come with problems for
you, the designer, to deal with; namely interfacing between the chips on
your board.  Sometimes it's easy, sometimes not.


> Next, where are the VIO pins(A10,A16,B19,A59,B59) supposed to
> connect to on the PCB?  The previous design I am looking at for a
> reference here
> just shows them bussed together and then coupled to GND.  I guess I don't
> quite
> understand what these pins do or how they relate to the signaling voltage
> of the
> card.
 
They should connect to some pins on your PCI interface chip.  They should
power the buffers in that chip that drive and receive the PCI signals.

It is a good idea to go from the connector pins to the chip pins through a
solid power plane, and add bypass capacitors where needed.

An alternative is to have an "island" in the power plane (or even a signal
plane), large enough to include the chip, connector pins, and bypass caps.
But avoid letting any signal traces cross over the "moat" (or island
boundary) on an adjacent layer.

The poorest choice is to run (fat) traces from the connector Vio pins to the
chip's Vio pins.  Bypass well at both ends.

If your card is keyed for 5V-only, or 3.3V-only, the Vio pins are identical
to the Vcc pins and can connect directly to the Vcc plane.

In some cases, your PCI chip might not even use Vio, except maybe to control
its overshoot clamp circuits.  These chips are designed to drive a 3.3V
waveform that is 5V-compatible, and to receive either 5V or 3.3V signals,
and use only 3.3V power ... except for the clamps which must be
Vio-dependent.

Regards,
Andy