PCI queries ( protocols + ASIC related )

["Ajit Madhekar" <ajit@controlnet.co.in>]

Hello pci-sig list members,

I have following queries

PCISIG section 3.5.1.1 says about target initial latency as 2^25 pci clocks
.
In this period the device ( network controller card ) is supposed to get the
boot image from the remote system.I have following doubts on this

1) How big is the OS image ? , because 2^25 clocks time comes to be 0.5 sec
for 66 mhz PCI clock rate. Assuming the packet driver code in boot ROM is
configuring a network controller ASIC for full duplex 100 Mbps mode then in
1/2 sec ,
6 Mega Bytes can be transferred on network.
What is the os image size that needs to be put in the system area thru PCI
cycles ?

2) If the device is not able to get the full image in the specified time ,
can it still pretend as bridge and give the remaining data with the latency
of 32 clocks after the frame assertion for each PCI cycle ?

3) My library supports following pads which are 5 Volt compatible
  PDBxDGZ(CMOS 3 state o/p pad with 5 v compatible where x stands for drive
capacity in mA) is used for CBE and AD .
     Now, for AD lines and other PCI signals, what is the needed drive
strength I have to keep ?
Also library has some pads PCI66DGZ  ( 3 state o/p 66 Mhz PCI buffer pad
with i/p and limited slew rate 5 volt tolerant ) which we used for s/t/s
signals
I observed the slew rates for both the mentioned pads and it is same 0.1 ns
.
Can I use the PDBxDGZ pad for all PCI bi-directional signals ?
or , I have to use the PCI66DGZ pad for s/t/s signals  ?

Regards,
Ajit Madhekar
Controlnet India Pvt Ltd
L-44, Unit 1 , STP
Verna Industrial Estate ,
Goa, India
www.controlnetindia.com