Address roll over !!

["Amit Shah" <Amit@dcmtech.com>]

Hi PCI experts,

I have a question related to PCI(X) address roll over.

Suppose a PCI(X) Bridge received a PMW transaction with a address of 
"4FFFFFFEh" (i.e. 2 bytes away from a internal 4096 boundary) and byte count of say 10.
Now a PCI(X) bridge cannot give a disconnect at ADB for this address (as the transaction is 1 data phase away from ADB), 
so it has to accept the transaction till min. of two ADB's.
(unlike in PCI mode, where it could have given a disconnect at 4096 boundary).

On the Destination bus, when the bridge initiated the transaction with the address of "4FFFFFFEh" , it received a
Single Data Phase Disconnect. So the Bridge has to re-initiate the transaction with the address of "50000000h".
For such a address change, the hardware will require a counter 32-bit. Now if a system is designed to have say 62-bit addressing, then
the hardware will require a counter of 62-bit for calculating the new address.

One more example of this problem would be a Spiltable Request.
Suppose a request came to a Bridge with a address of "4FFFFFFEh" and byte count of 10.
The Bridge will give a Split at the originating bus.
Now on the Destination bus, when the Bridge initiates the Request cycle, it receives a immediate completion with single
data phase disconnect, then the bridge will have to re-initiate the cycle with address of "50000000h"

The point that I am trying to raise is that how could I avoid such a huge counter for address calculations (in worst case
it could be a 64-bit counter) specifically in PCI-X mode.
Is there any way or constraint by which I could avoid the whole address roll over ?

Regards,

Amit Shah
Design Engr,
DCM Technologies
Austin