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Re: Address roll over !!
>>>Suppose a PCI(X) Bridge received a PMW transaction with a address of
"4FFFFFFEh" (i.e. 2 bytes away from a internal 4096 boundary) and byte
count of say 10.
Now a PCI(X) bridge cannot give a disconnect at ADB for this address (as
the transaction is 1 data phase away from ADB),
so it has to accept the transaction till min. of two ADB's.
(unlike in PCI mode, where it could have given a disconnect at 4096
Amit, A PCIX target is permitted to disconnect at the ADB even if the
starting address is one data phase away from the ADB. Is there some
different rule for PCIX bridges that says that the bridge is not allowed to
disconnect at ADB 1 data phase from the ADB?
>>>One more example of this problem would be a Spiltable Request.
Suppose a request came to a Bridge with a address of "4FFFFFFEh" and byte
count of 10.
The Bridge will give a Split at the originating bus.
Now on the Destination bus, when the Bridge initiates the Request cycle, it
receives a immediate completion with single
data phase disconnect, then the bridge will have to re-initiate the cycle
with address of "50000000h"
The point that I am trying to raise is that how could I avoid such a huge
counter for address calculations (in worst case
it could be a 64-bit counter) specifically in PCI-X mode.
Is there any way or constraint by which I could avoid the whole address
I don't see a way around having the large counter here. Are you worried
about the 64-bit counter using too many gates or the speed of the counter?
If speed, I know a way to make a 64-bit counter (incrementer) almost as
fast as a 32-bit. Email me.
IBM Microelectronics Division -- Austin
World Wide Field Design Center
Phone: 512-838-6305 Tie Line: 678-6305