Re: PCI 2.2 protocol question (FRAME# and Latency Timer timeout)

["Weng Tianxiang" <wtx@umem.com>]

Hi,
I think you violate PCI specs:
Once a master has asserted IRDY#, it cannot change IRDY# or FRAME# until the
current data phase completes regardless of the state of TRDY#.

The specs specifically mentions FRAME#, it means once master asserted IRDY#,
it determines to indicate two things: 1. current data is ready; 2. if it's
the last data.

>From hardware designer point of view, your design may have little effect on
other products. No design will fail to detect your state change while a
waiting cycle from Target is inserted

Weng Tianxiang
Micro Memory Inc.
9540 Vassar Av.
Chatsworth, CA 91311
Phone: 818-998-0070, Fax: 818-998-4459

----- Original Message -----
From: Simi Valecha <simi_valecha@yahoo.com>
To: <pci-sig@znyx.com>
Cc: <simi_valecha@znyx.com>
Sent: Friday, October 13, 2000 4:58 PM
Subject: Fwd: PCI 2.2 protocol question (FRAME# and Latency Timer timeout)


> I have a PCI protocol question for our PCI master
> design. We are getting a protocol violation if we use
> our vendor simulation monitor, but I am not sure if it
> a real problem or not. In case it is not a real
> problem, we would prefer not to change our RTL this
> late.
>
> The problem is the following:
> The master Latency Timer expires on cycle 2, while
> GNT# to the master is deasserted on cycle 2. Both
> IRDY# and FRAME# are asserted on cycle 2. However, the
> slave on the bus inserts a wait state here and
> deasserts TRDY# on cycle 2. Currently, our master
> deasserts FRAME# on the next cycle (cycle 3) while
> keeping IRDY# asserted. However, our EDA vendor
> monitor says that we are violating the following
> requirement: "Once a master has asserted IRDY# it
> cannot change FRAME# until the current data phase
> completes (3.2.1)".
>
> We think that there is no violation because the last
> line of the second paragraph on p.50 of the spec (Sec.
> 3.3.3.1) suggests that even if TRDY# was deasserted,
> FRAME# could be deasserted (as long as IRDY# is kept
> asserted).
> Can someone please clarify if it is safe for us not to
> change our design? And if we don't, what could be the
> potential implications? Or should we bit the bullet
> and change our RTL.
>
> Thanks a lot!
>
> -Simi
> simi_valecha@yahoo.com
>
>
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