AW: Byte Wide Devices on PCI Bus

["Preissner, Joachim" <joachim.preissner@actel.com>]

There is absolutely no issue with doing this. Using CBEs is the way.
But your backend needs to break the maximum 32bit incoming data down
into appropriate byte accesses (with diff. address LSB).
I guess you need to consider the bandwidth through the byte wide
bottleneck. This might lead you to using either some FIFO or implementing
posted write access and delayed transactions.

Joachim

-----Ursprüngliche Nachricht-----
Von: Markou, Pete [mailto:Pete.Markou@GD-CS.COM]
Gesendet am: Mo, 16. Okt 2000 23:16
An: 'pci-sig@znyx.com'
Betreff: Byte Wide Devices on PCI Bus

I'm looking into designing an embedded motherboard using FPGAs with a PCI
Core.   On the backend of the FPGA there will be some byte-wide memory
devices (i.e., flash, ram) organized as x8 not x32.   Since PCI memory space
is DWORD aligned, will there be any issues addressing byte-wide devices
(i.e., x8 Flash) over the PCI bus?    

I was assuming the FPGA design could encode the byte enables  "C/BE(3:0)"
into the 2 LSB address bits required by the byte-wide memory devices.  Again
the memory devices are organized as x8 not x32.   Is this assumption
correct?  

Thanks