Re: about protocol

[Kenneth_Chi-Yiu WONG <kcwong@ecr.mu.oz.au>]

Hi, just like to ask if there are any PCI interface chip that is not
restricted by the 8/16 clock delay constraint described below. Please
provide model number if possible.
And what is the exact number of clock cycles that the master wait for?
And does this means that there's no delayed transaction happening across
P2P bridge?

Thanks

Ken

On Tue, 17 Oct 2000, Mike Dini wrote:

> 
> >Suppose a TARGET violates the rule "The target must transfer the first 
> >data item within 16 clocks from the assertion of FRAME#  or within 8 
> >clocks for subsequent data phases" then what should be the MASTER'S action?
> >Can it deassert the FRAME# and IRDY# siganals and go to idle state?
> 
> The master should continue to wait for the data to be transferred.  After 
> some amount of time (thousands of clocks or more) the master should timeout 
> and go back to idle, but report an error to the master that requested the 
> transfer.
> 
> Note that bridges are not bound by this 8/16 delay.