PCI-PCI bridge

["Jim Chan" <tan264@hotmail.com>]

Hi guys,

THe Intel bridges 21555 support independent primary and secondary PCI 
clocks, how does this work??  What i mean is since now the PCI buses are 
running at different frequencies, for a write operation, if the data writing 
in at primary bus at a rate much faster than the rate of reading out at the 
secondary bus, then the buffer could be filled up easily. If the difference 
between the two buses frequencies are huge, than the whole process is going 
to be slow!!  Am I right?

Tan
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