Re: PCI-PCI bridge

["John D. Cappello" <jcappello@optimal-design.com>]

Tan,

I don't know much about that particular bridge but your logic is correct. By
definition, if the write side bandwidth (BW) is faster than the read side BW,
the write side needs to be throttled back somehow because the read side cannot
handle the full write side BW. Functionally, this is okay, your read side is
just a slower "peripheral."

The bridge should be able to throttle back the write side (probably via target
terminate and retry) until the read side has completed transfers that haven't
completed.

>From a system performance point of view, you may not want the write side to
blast long bursts of data at its full BW to this slower peripheral; it can cause
degradation of system performance on the primary side bus due to annoying
terminate/retries that hog the bus. Perhaps the source of these transfers can be
configured accordingly to burst data at a bandwidth that the peripheral can
handle.

Hope this helps.

John Cappello
Optimal Design, Inc.
856-582-4838
jcappello@optimal-design.com

Jim Chan wrote:

> Hi guys,
>
> THe Intel bridges 21555 support independent primary and secondary PCI
> clocks, how does this work??  What i mean is since now the PCI buses are
> running at different frequencies, for a write operation, if the data writing
> in at primary bus at a rate much faster than the rate of reading out at the
> secondary bus, then the buffer could be filled up easily. If the difference
> between the two buses frequencies are huge, than the whole process is going
> to be slow!!  Am I right?
>
> Tan
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