RE: PCI memory read line (MRL)

[Dave New <NewD@esi.com>]

This is a function of the CPU's north-bridge chipset.
There really isn't a special opcode in the x86
instruction set to signal such a read, so it would
be up to the north-bridge to somehow combine the reads
and produce the right request.  So far, Intel
has not supported anything like this.  On the
other hand, you can usually get short *write*
bursts using the CPU, if you have write-combining
turned on in the north-bridge chipset.

The rule of thumb for PCI burst transfers, is that
the source of the data must master the bus.  So,
if you wish to burst data from a board into the
CPU memory, you cannot use the CPU to do reads.
It will be terribly inefficient.  The best you will
be able to do will be word-size reads, with
lots of bus protocol overhead.  If you master
the bus with the board that has the data to send,
then you can do burst *writes* into the north-bridge
chipset.  All modern north-bridges support this,
but the maximum burst length varies.  It is
usually the cache-line length of the memory
interface behind the north-bridge, so it may
be only 16 or 32 bytes, or some other small
number.

This means that no matter what, you won't be
able to achieve that nirvana of PCI bus speed,
132 MBytes/sec.  Also, there is always CPU
contention for the memory behind the north-bridge,
which always gets top priority over incoming
PCI bus transfers.  Realistically, I've seen
maximum 80 MByte/sec transfers, and that was
only obtained by using bus mastering data sources.

Cheers,

- DaveN


-----Original Message-----
From: Max Lyadvinsky [mailto:ledmax@telecom.sins.ru]
Sent: Thursday, October 26, 2000 10:36 AM
To: 'PCI SIG'
Subject: PCI memory read line (MRL)


Dear All!

Does anybody know how to implement subj in a driver for WinNT? When I do
READ_REGISTER_BUFFER a simple memory read (MR) occurs.

Regards,
Max