North bridge functions

["Wood, Stephen" <swood07@harris.com>]

Gentlemen (and Ladies if any receive this reflector),

I've got a couple of questions about the operation of the North bridge in x86
based systems.

Question 1:

Does the North bridge "know" what BARs are used by the devices on the PCI bus?
For example, if the CPU generates a memory address, how does the North bridge
know if the reference is to main memory or a memory mapped device on the PCI
bus?

Question 2:

If I created a diagnostic device for the PCI bus that tried to remain
transparent, i.e. didn't respond to config commands and didn't have a memory or
I/O map, could it be a bus master at times.  What would happen if it asserted
REQ#?  Would it receive a GNT# from the arbiter?

Thanks for your help.

Steve