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Real-world disconnects



Hello, world

I have a strange question ?

As we all know, a target (the host PC memory) can ideally disconnect any
transaction on any data phase it likes.

Does anyone know what is the likeliness (or percentage rate) of the
current chipsets disconnecting a MWI on non-cacheline boundaries ?

Let me explain better:

My system starts a MWI whose length is multiple of one cacheline
(actually 8 or 16 dw).
What is the likeliness of the memory controller disconnecting this kind
of transaction not on cacheline boundaries ?

Of course any application must work in any case, but this is just for
some sort of profiling.

Thanks, Marco.



-- 
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 Marco BRAMBILLA   
            
 STMicroelectronics
 Via C. Olivetti, 2          
 20041 Agrate Brianza (MI)        
 ITALY                       
 
 TPA - Wireline Communications Division
 tel   : +39 039 603.5064   (ST Agrate - TINA 050 5064)
 tel   : +33 4 7658.5063    (ST Meylan - TINA 041 5063) 
 fax   : +33 4 7658.5410    (ST Meylan - TINA 041 5410)
 mailto:marco-tpa.brambilla@st.com
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