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Re: North bridge functions
> Question 1:
> Does the North bridge "know" what BARs are used by the devices on the PCI bus?
> For example, if the CPU generates a memory address, how does the North bridge
> know if the reference is to main memory or a memory mapped device on the PCI
There is usually a single boundary, maintained by the chipset, between
memory and PCI bus. All accesses below boundary => memory, accesses
=> PCI bus. The north bridge has no direct knowledge of any peripheral
device BAR programming.
> Question 2:
> If I created a diagnostic device for the PCI bus that tried to remain
> transparent, i.e. didn't respond to config commands and didn't have a memory or
> I/O map, could it be a bus master at times. What would happen if it asserted
> REQ#? Would it receive a GNT# from the arbiter?
It could be a master. It could receive GNT#. However, some chipsets
power-saving features which allow non-active PCI slots to be deactivated
(e.g. clock stopped, etc., possibly not polling REQ#.)
It would be a simple matter of identifying the offending chipsets and
reenabling all the clocks to insure your board was getting one.
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