Re: North bridge functions

[Patrick Maupin <pmaupin@jump.net>]

> Question 1:
> 
> Does the North bridge "know" what BARs are used by the devices on the PCI bus?
> For example, if the CPU generates a memory address, how does the North bridge
> know if the reference is to main memory or a memory mapped device on the PCI
> bus?

There is usually a single boundary, maintained by the chipset, between
memory and PCI bus.  All accesses below boundary => memory, accesses
above
=> PCI bus.  The north bridge has no direct knowledge of any peripheral
device BAR programming.

> Question 2:
> 
> If I created a diagnostic device for the PCI bus that tried to remain
> transparent, i.e. didn't respond to config commands and didn't have a memory or
> I/O map, could it be a bus master at times.  What would happen if it asserted
> REQ#?  Would it receive a GNT# from the arbiter?

It could be a master.  It could receive GNT#.  However, some chipsets
have
power-saving features which allow non-active PCI slots to be deactivated
(e.g. clock stopped, etc., possibly not polling REQ#.)

It would be a simple matter of identifying the offending chipsets and
reenabling all the clocks to insure your board was getting one.

-- 
Patrick Maupin
5216 Crooked Oak Cove
Austin, Texas 78749
512 891 6037