Re: Real-world disconnects

[Patrick Maupin <pmaupin@jump.net>]

For MWI, the controller must transfer entire cachelines,
according to the spec.  It is not allowed to stop on
a partial transfer.

Assuming linear addressing (and your controller could
refuse cachline wrap mode addressing if you only support
linear mode), the disconnect must always occur on a
cacheline boundary.

So, I cannot say what the percentage of broken controllers
is, but it _ought_ to approach 0%.

Pat


Marco Brambilla wrote:
> 
> Hello, world
> 
> I have a strange question ?
> 
> As we all know, a target (the host PC memory) can ideally disconnect any
> transaction on any data phase it likes.
> 
> Does anyone know what is the likeliness (or percentage rate) of the
> current chipsets disconnecting a MWI on non-cacheline boundaries ?
> 
> Let me explain better:
> 
> My system starts a MWI whose length is multiple of one cacheline
> (actually 8 or 16 dw).
> What is the likeliness of the memory controller disconnecting this kind
> of transaction not on cacheline boundaries ?
> 
> Of course any application must work in any case, but this is just for
> some sort of profiling.
> 
> Thanks, Marco.
> 
> --
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>  Marco BRAMBILLA
> 
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-- 
Patrick Maupin
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