Re: Real-world disconnects

[Duane Clark <dclark@akamail.com>]

The PCI spec (v2.2) section 3.1.2, second paragraph. To my mind, it
clearly states that a target may disconnect an MWI anywhere, not just on
a cacheline boundary. It is a different story for the master, which I
believe is required to complete the cacheline, if not stopped by the
target. And by the way, two paragraphs earlier, the spec requires the
MWI to use linear addressing.

Of course, this does not answer the original question of whether any
bridge chips, when acting as the target of a MWI, actually do this.
Which I have no idea about.

"James Lam(SC)" wrote:
> 
>     I couldn't find any information about MWI disconnect in the PCI spec
> (v2.2). However, in the PCI-to-PCI Bridge v1.1 spec, it did mention about it
> on page 73 section 5.2.1.4. In short, if the MWI is not disconnected in the
> boundary of the cacheline, the master should use the MW command for the rest
> of the data.
> 
> James Lam.
> 
> > ----------
> > From:         Patrick Maupin[SMTP:pmaupin@jump.net]
> > Sent:         Tuesday, October 31, 2000 9:56 AM
> > To:   pci-sig@znyx.com
> > Subject:      Re: Real-world disconnects
> >
> > For MWI, the controller must transfer entire cachelines,
> > according to the spec.  It is not allowed to stop on
> > a partial transfer.
> >
> > Assuming linear addressing (and your controller could
> > refuse cachline wrap mode addressing if you only support
> > linear mode), the disconnect must always occur on a
> > cacheline boundary.
> >
> > So, I cannot say what the percentage of broken controllers
> > is, but it _ought_ to approach 0%.
> >
> > Pat
> >
> >
> > Marco Brambilla wrote:
> > >
> > > Hello, world
> > >
> > > I have a strange question ?
> > >
> > > As we all know, a target (the host PC memory) can ideally disconnect any
> > > transaction on any data phase it likes.
> > >
> > > Does anyone know what is the likeliness (or percentage rate) of the
> > > current chipsets disconnecting a MWI on non-cacheline boundaries ?
> > >
> > > Let me explain better:
> > >
> > > My system starts a MWI whose length is multiple of one cacheline
> > > (actually 8 or 16 dw).
> > > What is the likeliness of the memory controller disconnecting this kind
> > > of transaction not on cacheline boundaries ?
> > >
> > > Of course any application must work in any case, but this is just for
> > > some sort of profiling.
> > >
> > > Thanks, Marco.