Re: Real-world disconnects

[Patrick Maupin <pmaupin@jump.net>]

Page 23, 3rd paragraph down (right before 3.1.2
"Command usage rules"):

"The memory write and invalidate command is semantically
identical to the memory write command except that it
additionally guarantees a minimum transfer of one cacheline;
ki.e. the master intends to write all bytes within the addressed
cacheline in a single PCI transaction unless interrupted by the
target.  Note: All byte enables must be asserted during each
data phase for this command.  The master may allow the transaction
to cross a cacheline boundary only if it intends to transfer the
entire next line also."


This seems to imply that the master is not allowed to
shorten the transaction, but the target could; and I
would agree that if the transaction is shortened, the
master should pick back up with MW (because the
cacheline has already been invalidated).

Pat

"James Lam(SC)" wrote:
> 
>     I couldn't find any information about MWI disconnect in the PCI spec
> (v2.2). However, in the PCI-to-PCI Bridge v1.1 spec, it did mention about it
> on page 73 section 5.2.1.4. In short, if the MWI is not disconnected in the
> boundary of the cacheline, the master should use the MW command for the rest
> of the data.
> 
> James Lam.
> 
> > ----------
> > From:         Patrick Maupin[SMTP:pmaupin@jump.net]
> > Sent:         Tuesday, October 31, 2000 9:56 AM
> > To:   pci-sig@znyx.com
> > Subject:      Re: Real-world disconnects
> >
> > For MWI, the controller must transfer entire cachelines,
> > according to the spec.  It is not allowed to stop on
> > a partial transfer.
> >
> > Assuming linear addressing (and your controller could
> > refuse cachline wrap mode addressing if you only support
> > linear mode), the disconnect must always occur on a
> > cacheline boundary.
> >
> > So, I cannot say what the percentage of broken controllers
> > is, but it _ought_ to approach 0%.
> >
> > Pat
> >
> >
> > Marco Brambilla wrote:
> > >
> > > Hello, world
> > >
> > > I have a strange question ?
> > >
> > > As we all know, a target (the host PC memory) can ideally disconnect any
> > > transaction on any data phase it likes.
> > >
> > > Does anyone know what is the likeliness (or percentage rate) of the
> > > current chipsets disconnecting a MWI on non-cacheline boundaries ?
> > >
> > > Let me explain better:
> > >
> > > My system starts a MWI whose length is multiple of one cacheline
> > > (actually 8 or 16 dw).
> > > What is the likeliness of the memory controller disconnecting this kind
> > > of transaction not on cacheline boundaries ?
> > >
> > > Of course any application must work in any case, but this is just for
> > > some sort of profiling.
> > >
> > > Thanks, Marco.
> > >
> > > --
> > > -------------------------------------------------------
> > >  Marco BRAMBILLA
> > >
> > >  STMicroelectronics
> > >  Via C. Olivetti, 2
> > >  20041 Agrate Brianza (MI)
> > >  ITALY
> > >
> > >  TPA - Wireline Communications Division
> > >  tel   : +39 039 603.5064   (ST Agrate - TINA 050 5064)
> > >  tel   : +33 4 7658.5063    (ST Meylan - TINA 041 5063)
> > >  fax   : +33 4 7658.5410    (ST Meylan - TINA 041 5410)
> > >  mailto:marco-tpa.brambilla@st.com
> > > -------------------------------------------------------
> >
> > --
> > Patrick Maupin
> > 5216 Crooked Oak Cove
> > Austin, Texas 78749
> > 512 891 6037
> >

-- 
Patrick Maupin
5216 Crooked Oak Cove
Austin, Texas 78749
512 891 6037