Re: Real-world disconnects

[Patrick Maupin <pmaupin@jump.net>]

Actually, I mis-read the post rather than the spec
(before my coffee:)

I thought he was building a target and was
worried about master controllers.

Pat


Gérard Roudier wrote:
> 
> On Tue, 31 Oct 2000, Patrick Maupin wrote:
> 
> > For MWI, the controller must transfer entire cachelines,
> > according to the spec.  It is not allowed to stop on
> > a partial transfer.
> >
> > Assuming linear addressing (and your controller could
> > refuse cachline wrap mode addressing if you only support
> > linear mode), the disconnect must always occur on a
> > cacheline boundary.
> 
> You seem to have misread the spec, unless I just misunderstood your
> posting. The master is not allowed to `terminate' the transaction with a
> partial cache line having been transmitted, but the target can
> `disconnect' on any data phase. Btw, if the master restarts a transfer
> disconnected in such a way, it must use a normal WRITE transaction,
> obviously.
> 
> The MWI may be useful for cache-able targets that gain advantage on full
> cache line invalidations. Even if it has cache, a target may be unable to
> gain advantage of MWI. We can also imagine targets that do invalidate a
> full cacheline at a time on MWI, but can also `disconnect' inside a cache
> line and maintain coherency for the partially transmitted cache line.
> 
> This let me say that a cache-able target disconnecting a MWI on a partial
> cacheline must be considered as a quite normal situation by a PCI
> initiator, even if it may well be unusual in practice.
> 
> > So, I cannot say what the percentage of broken controllers
> > is, but it _ought_ to approach 0%.
> 
> Marco's posting does not seem to address any PCI controller flaw.
> Hmmm.. About the ratio of broken PCI controllers, it could well be closed
> to 100% rather than 0%, in my opinion. :-)
> 
> Regards,
>   Gérard.
> 
> >
> > Pat
> >
> >
> > Marco Brambilla wrote:
> > >
> > > Hello, world
> > >
> > > I have a strange question ?
> > >
> > > As we all know, a target (the host PC memory) can ideally disconnect any
> > > transaction on any data phase it likes.
> > >
> > > Does anyone know what is the likeliness (or percentage rate) of the
> > > current chipsets disconnecting a MWI on non-cacheline boundaries ?
> > >
> > > Let me explain better:
> > >
> > > My system starts a MWI whose length is multiple of one cacheline
> > > (actually 8 or 16 dw).
> > > What is the likeliness of the memory controller disconnecting this kind
> > > of transaction not on cacheline boundaries ?
> > >
> > > Of course any application must work in any case, but this is just for
> > > some sort of profiling.
> > >
> > > Thanks, Marco.
> > >
> > > --
> > > -------------------------------------------------------
> > >  Marco BRAMBILLA
> > >
> > >  STMicroelectronics
> > >  Via C. Olivetti, 2
> > >  20041 Agrate Brianza (MI)
> > >  ITALY
> > >
> > >  TPA - Wireline Communications Division
> > >  tel   : +39 039 603.5064   (ST Agrate - TINA 050 5064)
> > >  tel   : +33 4 7658.5063    (ST Meylan - TINA 041 5063)
> > >  fax   : +33 4 7658.5410    (ST Meylan - TINA 041 5410)
> > >  mailto:marco-tpa.brambilla@st.com
> > > -------------------------------------------------------
> >
> > --
> > Patrick Maupin
> > 5216 Crooked Oak Cove
> > Austin, Texas 78749
> > 512 891 6037
> >

-- 
Patrick Maupin
5216 Crooked Oak Cove
Austin, Texas 78749
512 891 6037