Re: Real-world disconnects

[Marco Brambilla <marco-tpa.brambilla@st.com>]

Hi Gerard,

> The MWI may be useful for cache-able targets that gain advantage on full
> cache line invalidations. Even if it has cache, a target may be unable to
> gain advantage of MWI. We can also imagine targets that do invalidate a
> full cacheline at a time on MWI, but can also `disconnect' inside a cache
> line and maintain coherency for the partially transmitted cache line.

I think MWI is especially useful when you're a master and want to move
data to host RAM without being interrupted.

But of course no target (the mem controller in this case) is obliged to
actually implement MWI, so it can as well alias it to the "normal"
write, as we all know.

> This let me say that a cache-able target disconnecting a MWI on a partial
> cacheline must be considered as a quite normal situation by a PCI
> initiator, even if it may well be unusual in practice.

Yes. For sure one situation your master must be aware of (and if it is
not, then it is broken ;)

> Marco's posting does not seem to address any PCI controller flaw.

Yap. That's right.

This behaviour is perfectly compliant with the PCI standard.

My question comes from profiling issues: I have a master device, which
moves to and from RAM at least 4 channels of data + 2 of control.

This means that you have to identify a good priority scheme and verify
the impact of bus behaviour in the drivers.

Not that I expect a MWI disconnect to be of much impact, this is most
for the sake ok information.

But if you think of a highly loaded system, if the mem controller
disconnects after few (2/3) data phases, this can have an impact in
system performances, especially if the latency is high on the bus.

Ciao, Marco.

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