Re: Real-world disconnects

[Patrick Maupin <pmaupin@jump.net>]

Again, I mis-read the original question, thinking
it was about building a target and worrying about
master behavior, when really it was about building
a master and worrying about target behavior.

A target does not have to disconnect at a cacheline
boundary, but a master does.  So, yes, a target could
alias the MWI command to MW, but a master should never
issue MWI if it does not intend to replace an entire
cacheline.

The result (which I think you are alluding to) is that
a master issuing a MWI has to be prepared for the target
to disconnect on a non-cacheline boundary.  In the event
this occurs, the master should finish out that particular
cacheline with a MW command instead of a MWI command.  It
is up to the master whether to continue on to the next
cacheline with the same MW command, or whether to revert
to an MWI command.

I would think that if there was still a lot of data to
be transferred, it might be advantageous to revert to
MWI after using MW to get back to a cacheline boundary,
but, obviously, if the target controller does not use
the extra information in MWI to avoid a cacheline load,
the overhead of issuing two separate commands when
restarting the transfer (MW, then MWI) is wasted.

In some cases, this overhead will be trivial, but in
other cases it could be quite substantial.  A simple,
automated way to compensate for the overhead could be
to count the number of cycles in the current burst.

Whenever you restart, if you are starting on a cacheline
boundary, use MWI.  If the number of cycles in the previous
burst is above some threshold value, use MW, then MWI.
If the number of cycles was below the threshold, juse use
MW, because you probably won't transfer enough data to
make issuing two commands worthwhile.

Regards,
Pat


Marco Brambilla wrote:
> 
> Hi Pat,
> 
> > For MWI, the controller must transfer entire cachelines,
> > according to the spec.  It is not allowed to stop on
> > a partial transfer.
> 
> Except if it is a (poor) controller which does not really implement MWI
> and aliases it to "standard" mem write.
> So the question would be:
> Are really there poor chipsets which do not implement MWI but rather
> alias it to MW (as per the PCI spec) ?
> 
> Ciao, Marco.
> --
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> 
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-- 
Patrick Maupin
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Austin, Texas 78749
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