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Re: Real-world disconnects



Hi Pat,

> master behavior, when really it was about building
> a master and worrying about target behavior.

Actually, this is not even worrying.
The behaviour to keep is (to me) well specified in the PCI spec.

The scenario is this:

master, different (4/5) "channels".
each channel moves data into bursts that last one or more cachelines
(but always in multiple of a cacheline)

Some priority scheme is implemented in order to allow handling of data
with different latency requirements.

It would be nice to have a figure of how likely the event of getting a
disconnect non cacheline-aligned, just to have an idea of the overhead.
Since I only have cacheline-size bursts I only care about this
particular kind of disconnect.

Ciao, Marco.

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