RE: 64 Bit Base Address Register

["O'Shea, David J" <david.j.oshea@intel.com>]

Although not very clear in the spec ( I would say needs revision )
The format is:


P = Prefetch Bit
TYPE = Size of BAR/Allowable location of BAR.
	if TYPE = 00, 01  then BAR = 4 bytes config space.
	if TYPE = 10      then BAR = 8 bytes config space.
--------
	if TYPE = 00 addr can be anywhere in 0-4GB
	if TYPE = 01 addr can be anywere in 0-1MB
	if TYPE = 10 addr can be anywhere in 0- 2^64 bytes.

                                                 Offset 
------------------------------------------------  10h   1ST BAR
Addr[31:4]					| P|TYPE| 0|
						  0   10  0  = 64 bit BAR
LSB [31:0] of the ADDR.  ADDR[3:0] ALWAYS 0!!!!
------------------------------------------------  14h
Addr[63:32]	      The whole higher offset 4 bytes
of configuration space is the MSB's of the addr.
------------------------------------------------  18h   2ND BAR
Addr[31:4]					| P|TYPE| 0|
                                      0   00  0 = 32 bit BAR
------------------------------------------------  1Ch   3RD BAR
Addr[31:4]					| P|TYPE| 0|
						  0   10  0  = 64 bit BAR
LSB [31:0] of the ADDR.  ADDR[3:0] ALWAYS 0!!!!
------------------------------------------------  20h   
Addr[63:32]	      The whole higher offset 4 bytes
of configuration space is the MSB's of the addr.
------------------------------------------------  24h   4th BAR
Addr[31:4]					| P|TYPE| 0|
                                      0   00  0 = 32 bit BAR
------------------------------------------------  28h


So, the special bits BAR[3:0] are only special on
the 1st "half" of the 64-bit Bar.  On the second
half, shown in this example as starting at 14h for
the 1ST BAR, which is 64-bits in size, the bits located
at 14h[3:0] are not special, they are just part of the
decoded address bits.  Another way to say it is that
BAR[35:32] of a 64bit BAR are not special, they are just
address bits. 

The impact of this method is that:
	Software always has to check the bits
	at 10h[3:0] to determine if the 1st BAR
	is 32bits or 64bits.  It interprets the BAR,
	and ALSO determines where the start of the
	next BAR is.   For instance, here its at 18h.
	It then checks 30h[3:0], to determine size,
	intepret that BAR and determine the start of
	the next BAR.

So, the 64bits BAR's are NOT just two copies
of the 32bit BAR's, that are intepreted in some
magical way.  The format just includes 32 more
upper address bits.  

Cheers,

David O'Shea




-----Original Message-----
From: Olaf Reichenbaecher [mailto:Olaf.Reichenbaecher@sci-worx.com]
Sent: Thursday, November 02, 2000 6:07 AM
To: pci-sig@znyx.com
Subject: 64 Bit Base Address Register


hi there,

i am currently dealing with the issue to design a 32-bit PCI
interface module which supports 64-bit addressing (DAC).
i am wondering what the topology of the BARs in the CS header
looks like.
assuming an address space of 2GB or less which may be located
anywhere in the 64-bit address space, the BAR pointing to that
address space has to implement 33 or more (dependent on the
actual size) read-write bits.
is this accomplished by "concatenating" 2 subsequent 32-bit BARs
in the CS header? which one would be the upper part (bits 63:32),
which one the lower (bits 31:0). which of the "concatenated"
BARs features the indicator fields (prefetch/type/mem-io)?
does that mean a PCI function may only claim a maximum of
3 base address spaces if all of them may be located
anywhere in the 64-bit address space?

although i scanned through the archive and found a number
of valuable information this issue is quite unclear to me.
even the spec was not of much help.

can someone please shade some light on this? any help
appreciated.

regards

  olaf
-- 
Olaf Reichenbaecher
Senior Design Engineer
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